Field of the Invention
The invention relates to a read-only memory cell configuration and a method for the production of a read-only memory cell configuration including a substrate formed of semiconductor material and having memory cells disposed in a cell field in a region of a main area, each memory cell having at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, the drain region connected to a bit line, the gate electrode connected to a word line, and the MOS transistor formed by a trench starting at the main area of the substrate and reaching as far as the source region.
Such a read-only memory cell configuration and such a method for its production are described, for example, in German Published, Non-Prosecuted Patent Applications DE 44 34 725 A1 and DE 44 37 581 A1, having the same assignee as the instant application and to which reference is fully made. Read-only memories are used to store data in many electronic systems. Such memories, in which the data are written-in permanently in digital form, are realized as silicon circuits that have an integrated construction based on a semiconductor material, in particular silicon, and in which MOS transistors are preferably used as memory cells. During read-out, the individual memory cells are selected through the gate electrode of the MOS transistors, which is connected to a word line. The input of each MOS transistor is connected to a reference line and the output is connected to a bit line. During the reading operation, an assessment is made as to whether or not a current is flowing through the transistor. Logic values 0 and 1 are assigned correspondingly to the stored data. The storage of 0 and 1 in such read-only memories is effected in technical terms in such a way that no MOS transistor is produced or no conductive connection to the bit line is realized in memory cells in which the logic value assigned to a state "no current flow through the transistor" is stored. As an alternative, MOS transistors which have different threshold voltages due to different implantations in the channel region can be correspondingly realized for the two logic values. Such a silicon memory has an essentially planar structure with a minimum area requirement for each memory cell, which is about 4 to 8 F.sup.2, where F denotes the smallest structure size that can be produced with the respective technology. In the case of one-.mu.m technology, planar read-only silicon memories are thus limited to storage densities of about 0.14 bit/.mu.m.sup.2.